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PCA9512 Level shifting hot swappable I2C and SMBus buffer
Product data sheet 2004 Oct 05
Philips Semiconductors
Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
DESCRIPTION
The PCA9512 is a hot swappable I2C and SMBus buffer that allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9512 provides bi-directional buffering, keeping the backplane and card capacitances isolated. The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers allow them to be connected to another PCA9510/11/12/13/14 device in series or in parallel and to the A side of the PCA9517. The PCA9510/11/12/13/14 can not connect to the static offset I/Os used on the PCA9515/15A/16/16A/17 B side and PCA9518.
PIN CONFIGURATION
TOP VIEW VCC2 1 SCLOUT SCLIN GND 2 3 4 8 7 6 5 VCC SDAOUT SDAIN ACC
FEATURES
* Bi-directional buffer for SDA and SCL lines increases fanout and * Compatible with I2C standard mode, I2C fast mode, and SMBus
standards to disable V/t rise time accelerators through the ACC pin for lightly loaded systems prevents SDA and SCL corruption during live board insertion and removal from multi-point backplane systems Figure 1. Pin configuration.
SW02070
PIN DESCRIPTION
PIN 1 SYMBOL VCC2 DESCRIPTION Supply voltage for devices on the card I2C-buses. Connect pull-up resistors from SDAOUT and SCLOUT to this pin. Serial clock output to and from the SCL bus on the card. Serial clock input to and from the SCL bus on the backplane. Ground. Connect this pin to a ground plane for best results. CMOS threshold digital input pin that enables and disables the rise-time accelerators on all four SDA and SCL pins. ACC enables all accelerators when set to VCC2, and turns them off when set to GND. Serial data input to and from the SDA bus on the backplane/long distance bus. Serial data output to and from the SDA bus on the card. Power supply. From the backplane, connect pull-up resistors from SDAIN and SCLIN to this pin.
* V/t rise time accelerators on all SDA and SCL lines with ability * 5 V to 3.3 V level translation with optimum noise margin * High-impedance SDA, SCL pins for VCC or VCC2 = 0 V * 1 V precharge on all SDA and SCL lines * Supports clock stretching and multiple master
arbitration/synchronization
2 3 4 5
SCLOUT SCLIN GND ACC
* Operating power supply voltage range: 2.7 V to 5.5 V * 5.5 V tolerant I/Os * 0 kHz to 400 kHz clock frequency * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latch-up testing is done to JESDEC Standard JESD78 which * Packages offered: SO8, TSSOP8 (MSOP8)
APPLICATION
exceeds 100 mA 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
6 7 8
SDAIN SDAOUT VCC
* cPCI, VME, AdvancedTCA cards and other multi-point backplane
cards that are required to be inserted or removed from an operating system.
ORDERING INFORMATION
PACKAGES 8-pin plastic SO 8-pin plastic TSSOP (MSOP) TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C ORDER CODE PCA9512D PCA9512DP TOPSIDE MARK PCA9512 9512 DRAWING NUMBER SOT96-1 SOT505-1
Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
2004 Oct 05
2
Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
TYPICAL APPLICATION
VCC 5V R1 10 k R2 10 k C2 0.01 F C1 0.01 F R3 10 k R4 10 k R5 10 k CARD_VCC 3 V
VCC SDA SDAIN
VCC2 SDAOUT CARD_SDA
SCL
SCLIN
SCLOUT
CARD_SCL C5* 0.01 F
C3* 0.01 F
C4* 0.01 F
PCA9512
GND
ACC
C6* 0.01 F
* CAPACITORS NOT REQUIRED IF BUS IS SUFFICIENTLY LOADED
SW02068
Figure 2. Typical application
BLOCK DIAGRAM
VCC 8 2 mA SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT 100 k RCH1 1 VOLT PRECHARGE 100 k RCH2 2 mA SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT CONNECT 2 mA SLEW RATE DETECTOR 2 100 k RCH4 CONNECT CONNECT 100 k RCH3 2 mA SLEW RATE DETECTOR 7 1 VCC2
ACC
SDAIN 6
SDAOUT
ACC
5
ACC
SCLIN 3
SCLOUT
0.5 A 0.55VCC/ 0.45VCC 95 s DELAY
STOP BIT AND BUS IDLE
0.55VCC/ 0.45VCC
20 pF UVLO RD QB S
CONNECT
CONNECT
UVLO
4 0.5 pF
GND
SW02069
Figure 3. Block diagram.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
FEATURE SELECTION CHART
FEATURES Idle detect High impedance SDA, SCL pins for VCC = 0 V Rise time accelerator circuitry on all SDA and SCL lines Rise time accelerator circuitry hardware disable pin for lightly loaded systems Rise time accelerator threshold 0.8 V vs 0.6 V improves noise margin Ready open drain output Two VCC pins to support 5 V to 3.3 V level translation with improved noise margins 1 V precharge on all SDA and SCL lines 92 A current source on SCLIN and SDAIN for PICMG applications PCA9510 Yes Yes -- -- -- Yes -- IN only -- PCA9511 Yes Yes Yes -- -- Yes -- Yes -- PCA9512 Yes Yes Yes Yes -- -- Yes Yes -- PCA9513 Yes Yes Yes -- Yes Yes -- -- Yes PCA9514 Yes Yes Yes -- Yes Yes -- -- --
OPERATION Start-up
When the PCA9512 is powered up either VCC or VCC2 may rise first and either may be more positive or they may can be equal, however the PCA9512 will not leave the under voltage lock out/initialization state until both VCC and VCC2 have gone above 2.5 V. If either VCC or VCC2 drops below 2.0 V it will return to the under voltage lock out/initialization state. In the under voltage lock out state the connection circuitry is disabled, the rise time accelerators are disabled, and the precharge circuitry is also disabled. After both VCC and VCC2 are valid, independent of which is higher, the PCA9512 enters the initialization state, during this state the 1 V precharge circuitry is activated and pulls up the SDA and SCL pins to 1 V through individual 100 k nominal resistors. At the end of the initialization state the "Stop Bit And Bus Idle" detect circuit is enabled. When all the SDA and SCL pins have been HIGH for the bus idle time or when all pins are HIGH and a stop condition is seen on the SDAIN and SCLIN pins, the connect circuitry is activated, connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V precharge circuitry is disabled when the connection is made, unless the ACC pin is LOW, the rise time accelerators are enabled at this time also.
Connection Circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that isolated the input bus capacitance from the output bus capacitance while communicating the logic levels. If VCC VCC2, then a level shifting function is also performed between input and output. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be driven LOW by the
PCA9512. The same is also true for the SCL pins. Noise between 0.7VCC and VCC on the SDAIN and SCLIN pins and 0.7VCC2 and VCC2 on the SDAOUT and SCLOUT pins is generally ignored because a falling edge is only recognized when it falls below the 0.7VCC for SDAIN and SCLIN (or 0.7VCC2 for SDAOUT and SCLOUT pins) with a slew rate of at least 1.25 V/s. When a falling edge is seen on one pin the other pin in the pair turns on a pull down driver that is reference to a small voltage above the falling pin. The driver will pull the pin down at a slow rate determined by the driver and the load. The first falling pin may have a fast or slow slew rate, if it is faster than the pull down slew rate then the initial pull down rate will continue until it is LOW. If the first falling pin has a slow slew rate then the second pin will be pulled down at its initial slew rate only until it is just above the first pin voltage then they will both continue down at the slew rate of the first. Once both sides are LOW they will remain LOW until all the external drivers have stopped driving LOWs. If both sides are being driven LOW to the same or nearly the same value by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving, that pin will rise and rise above the nominal offset voltage until the internal driver catches up and pulls it back down to the offset voltage. This bounce is worst for low capacitances and low resistances, and may become excessive. When the last external driver stops driving a LOW, that pin will bounce up and settle out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the RC time constant. As long as the slew rate is at least 1.25 V/s, when the pin voltage exceed 0.6 V the rise time accelerator circuits are turned on and the pull down driver is turned off. If the ACC pin is LOW the rise time accelerator circuits will be disabled but the pull down driver will still turn off.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
Maximum number of devices in series
Each buffer adds about 0.065 V dynamic level offset at 25 C with the offset larger at higher temperatures. Maximum offset (VOS) is 0.150 V. The LOW level at the signal origination end (master) is dependent upon the load and the only specification point is the I2C-bus specification of 3 mA will produce VOL < 0.4 V, although if lightly loaded the VOL may be 0.1 V. Assuming VOL = 0.1 V and VOS = 0.1 V, the level after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the rising edge accelerator (about 0.6 V). With great care a system with four buffers may work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing the rising edge accelerator thus introducing false clock edges. Generally it is recommended to limit the number of buffers in series to two. The PCA9510 (rise time accelerator is permanently disabled) and the PCA9512 (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull-down off. If the VIL is above 0.6 V and a rising edge is detected, the pull-down will turn off and will not turn back on until a falling edge is detected; so if the noise is small enough it may be possible to use more than two PCA9510 or PCA9512 parts in series but is not recommended.
is the only part driving the node. The common node will rise to 0.5 V before Buffer B's output turns on, if the pull-up is strong the node will bounce. If the bounce goes above the threshold for the rising edge accelerator 0.6 V the accelerators on both Buffer A and Buffer C will fire contending with the output of Buffer B. The node on the input of Buffer A will go HIGH as will the input node of Buffer C. After the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to 0.5 V because the Buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to 0.6 V until Slave B turned off. This would not cause a failure on the data line as long as the return to 0.5 V on the common node (0.6 V at the Master and Slave C) occurred before the data setup time. If this were the SCL line, the parts on Buffer A and Buffer C would see a false clock rather than a stretched clock, which would cause a system error.
Propagation Delays
The delay for a rising edge is determined by the combined pull-up current from the bus resistors and the PCA9512 and the effective capacitance on the lines. If the pull-up currents are the same, any difference in capacitance between the two sides. The tPLH may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. The tPHL can never be negative because the output does not start to fall until the input is below 0.7VCC (or 0.7VCC2 for SDAOUT and SCLOUT) and the output pull down turn on has a nonzero delay, and the output has a limited maximum slew rate and even it the input slew rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage, The maximum tPHL occurs when the input is driven LOW with zero delay and the output is still limited by its turn on delay and the falling edge slew rate, The output falling edge slew rate (which is a function of temperature, VCC or VCC2, and process) as well as load current and load capacitance.
buffer A MASTER common node
buffer B SLAVE B
buffer C SLAVE C
SW02353
Figure 4. Consider a system with three buffers connected to a common node and communication between the Master and Slave B that are connected at either end of Buffer A and Buffer B in series as shown in Figure 4. Consider if the VOL at the input of Buffer A is 0.3 V and the VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to Slave B and then from Slave B to Master. Before the direction change you would observe VIL at the input of Buffer A of 0.3 V and its output, the common node, is 0.4 V. The output of Buffer B and Buffer C would be 0.5 V, but Slave B is driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of Buffer C is 0.5 V. When the Master pull-down turns off, the input of Buffer A rises and so does its output, the common node, because it
Rise Time Accelerators
During positive bus transitions a 2 mA current source is switched on to quickly slew the SDA and SCL lines HIGH once the input level of 0.6 V is exceeded. The rising edge rate should be at least 1.25 V/s to guarantee turn on of the accelerators.
ACC Boost Current Enable
Users having lightly loaded systems may wish to disable the rise-time accelerators. Driving this pin to ground turns off the rise-time accelerators on all four SDA and SCL pins. Driving this pin to the VCC2 voltage enables normal operation of the rise-time accelerators.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
Resistor Pull-up Value Selection
The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 V/s on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value using the formula: R (VCC(MIN) - 0.6) (800,000)/C where R is the pull-up resistor value in ohms, VCC(MIN) is the minimum VCC voltage and C is the equivalent bus capacitance in picofarads (pF). In addition, regardless of the bus capacitance, always choose R 16 k for VCC = 5.5 V maximum, R 24 k for VCC = 3.6 V maximum. The start-up circuitry requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. See the curves in Figures 5 and 6 for guidance in resistor pull-up selection.
30 RPULLUP (k) 25 RMAX = 24 k 20 21 RECOMMENDED PULL-UP 5 20 RPULLUP (k) 15 RMAX = 16 k RISE-TIME > 300 ns
0 0 100 200 CBUS (pF) 300 400
SW02116
Figure 6. Bus requirements for 5 V systems
Minimum SDA and SCL Capacitance Requirements
RISE-TIME > 300 ns
15
21 RECOMMENDED PULL-UP 5
0 0 100 CBUS (pF) 200 300 400
SW02115
Figure 5. Bus requirements for 3.3 V systems
The device connection circuitry requires a minimum capacitance loading on the SDA and SCL pins in order to function properly. The value of this capacitance is a function of VCC and the bus pull-up resistance. Estimate the bus capacitance on both the backplane and the card data and clock buses, and refer to Figures 5 and 6 to choose appropriate pull-up resistor values. Note from the figures that 5 V systems should have at least 47 pF capacitance on their buses and 3.3 V systems should have at least 22 pF capacitance for proper operation of the PCA9512. Although the device has been designed to be marginally stable with smaller capacitance loads, for applications with less capacitance, provisions need to be made to add a capacitor to ground to ensure these minimum capacitance conditions if oscillations are noticed during initial signal integrity verification.
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
Hot Swapping and Capacitance Buffering Application
Figures 7 through 9 illustrate the usage of the PCA9512 in applications that take advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to meet. Placing a
PCA9512 on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the PCA9512 drives the capacitance of everything on the card and the backplane must drive only the the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and all additional cards on the backplane. See Application Note AN10160, Hot Swap Bus Buffer for more information on applications and technical assistance.
BACKPLANE CONNECTOR BACKPLANE STAGGERED CONNECTOR VCC2 BD_SEL VCC SDA SCL R1 10 k R2 10 k POWER SUPPLY HOT SWAP I/O PERIPHERAL CARD 1
C1 0.01 F
R4 10 k
R5 10 k
R6 10 k CARD1_SDA CARD1_SCL
R3 5.1
VCC SDAIN SCLIN
VCC2
SDAOUT SCLOUT ACC
PCA9512
GND
C2 0.01 F
I/O PERIPHERAL CARD 2 POWER SUPPLY HOT SWAP
STAGGERED CONNECTOR
C3 0.01 F
R8 10 k
R9 10 k
R10 10 k
CARD2_SDA CARD2_SCL
R7 5.1
VCC SDAIN SCLIN
VCC2
SDAOUT SCLOUT ACC
PCA9512
GND
C4 0.01 F
I/O PERIPHERAL CARD N STAGGERED CONNECTOR POWER SUPPLY HOT SWAP
C5 0.01 F
R12 10 k
R13 10 k
R14 10 k CARDN_SDA CARDN_SCL
R11 5.1
VCC SDAIN SCLIN
VCC2
SDAOUT SCLOUT ACC
PCA9512
GND
C6 0.01 F
SW02117
NOTE: Application assumes bus capacitance within "proper operation" region of Figures 5 and 6. Figure 7. Hot swapping multiple I/O cards into a backplane using the PCA9512 in a CompactPCI, VME, and AdvancedTCA system
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
BACKPLANE CONNECTOR BACKPLANE STAGGERED CONNECTOR VCC2 I/O PERIPHERAL CARD 1
C1 0.01 F R3 5.1
R4 10 k
R5 10 k
R6 10 k CARD1_SDA CARD1_SCL
VCC SDA SCL R1 10 k R2 10 k
VCC SDAIN SCLIN
VCC2
SDAOUT SCLOUT ACC
PCA9512
GND
C2 0.01 F
I/O PERIPHERAL CARD 2
STAGGERED CONNECTOR
C3 0.01 F R4 5.1
R8 10 k
R9 10 k
R10 10 k CARD2_SDA CARD2_SCL
VCC SDAIN SCLIN
VCC2
SDAOUT SCLOUT ACC
PCA9512
GND
C4 0.01 F
SW02118
NOTE: Application assumes bus capacitance within "proper operation" region of Figures 5 and 6. Figure 8. Hot swapping multiple I/O cards into a backplane using the PCA9512 with a custom connector
VCC 5 V R1 10 k SCL SCL R4 10 k C2 0.01 F C1 0.01 F R3 10 k R2 10 k CARD_SDA CARD_SCL
CARD_VCC, 3 V
SDAIN SCLIN
VCC
VCC2
SDAOUT SCLOUT ACC
PCA9512
GND
SW02119
NOTE: Application assumes bus capacitance within "proper operation" region of Figures 5 and 6. Figure 9. 5 V to 3.3 V level translator and bus buffer
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
ABSOLUTE MAXIMUM RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134). Voltages with respect to pin GND. LIMITS SYMBOL VCC VCC2 Vn II IIO Topr Tstg Tsld Tj(max) Supply voltage range VCC Supply voltage range VCC2 SDAIN, SCLIN, SDAOUT, SCLOUT, ACC Maximum current for inputs Maximum current for I/O pins Operating temperature range Storage temperature range Lead soldering temperature (10 sec max) Maximum junction temperature PARAMETER MIN. -0.5 -0.5 -0.5 - - -40 -65 -- -- MAX. +7 +7 +7 20 50 +85 +125 +300 +125 UNIT V V V mA mA C C C C
NOTE: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
ELECTRICAL CHARACTERISTICS
VCC = 2.7 V to 5.5 V; Tamb = -40 C to +85 C unless otherwise noted. SYMBOL Power supply VCC VCC2 IVCCI IVCC2 VPRE tEN tIDLE IPULLUPAC Supply voltage Card side supply voltage VCC supply current VCC supply current Precharge voltage Enable time on power-up Bus idle time Transient boosted pull-up current Note 1. Note 1. VCC = 5.5 V; VSDAIN = VSCLIN = 0 V VCC = 5.5 V; VSDAOUT = VSCLOUT = 0 V SDA, SCL floating; Note 1. Note 6. Notes 1 and 7. Positive transition on SDA, SCL, ACC = 0.7 V x VCC2; VCC = 2.7 V; Slew rate = 1.25 V/s; Note 2. 2.7 2.7 -- -- 0.8 -- 50 1 -- -- 1.2 1.1 1.1 180 140 2 5.5 5.5 3.6 2.4 1.2 -- 250 -- V V mA mA V s s mA PARAMETER TEST CONDITIONS LIMITS MIN. TYP. MAX. UNIT
Start-up circuitry
Rise time accelerators
VACCDIS VACCEN IVACC tPDOFF VOS
Accelerator disable threshold Accelerator enable threshold ACC input current ACC delay, on/off Input-output offset voltage 10 k to VCC on SDA, SCL; VCC = 3.3 V, VCC2 = 3.3 V; VIN = 0.2 V; Note 1; Note 3. Guaranteed by design, not subject to test Guaranteed by design, not subject to test Input = 0 V. SDA, SCL pins; ISINK = 3 mA; VCC = 2.7 V; VCC2 = 2.7 V; Note 1. SDA, SCL pins = VCC = 5.5 V; VCC2 = 5.5 V Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Notes 4 and 5 Notes 4 and 5
0.3 x VCC2 -- -1 -- 0
0.5 x VCC2 0.5 x VCC2 0.1 5 70
-- 0.7 x VCC2 1 -- 150
V V A ns mV
Input-output connection
fSCL_SDA CIN VOL
operating frequency Digital input capacitance LOW-level output voltage
0 -- 0
-- -- --
400 10 0.4
kHz pF V
ILI
Input leakage current
-1
--
5
A
Timing characteristics fI2C tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tSU;DAT tLOW tHIGH tf tr I2C operating frequency Bus free time between stop and start condition Hold time after (repeated) start condition Repeated start condition setup time Stop condition setup time Data hold time Data setup time Clock LOW period Clock HIGH period Clock, data fall time Clock, data rise time 0 1.3 0.6 0.6 0.6 300 100 1.3 0.6 20 + 0.1 x CB 20 + 0.1 x CB -- -- -- -- -- -- -- -- -- -- -- 400 -- -- -- -- -- -- -- -- 300 300 kHz s s s s ns ns s s ns ns
NOTES: 1. This specification applies over the full operating temperature range. 2. IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section.
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
3. The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pull-up resistor and VCC voltage is shown in the Typical Performance Characteristics section. 4. Guaranteed by design, not production tested. 5. CB = total capacitance of one bus line in pF. 6. Enable time is from power-up of VCC and VCC2 2.7 V to when idle or stop time begins. 7. Idle time is from when SDAx and SCLx are HIGH after enable time has been met.
TYPICAL PERFORMANCE CHARACTERISTICS
1.5 1.4 1.3 VCC = 5.5 V 1.2 I CC (mA) 1.1 VCC = 2.7 V 1.0 0.9 0.8 0.7 -40 +25 TEMPERATURE (C) +85 380 CIN = COUT = 100 pF RPULLUPIN = RPULLUPOUT = 10 k -40 +25 TEMPERATURE (C) +85 (ns) VCC = 3.3 V 420 VCC = 5.5 V 440 460 VCC = 2.7 V
t
PHL
VCC = 3.3 V 400
SW02343
SW02344
Figure 10. ICC versus Temperature (Note 1)
12
Figure 12. Input-output tPHL versus Temperature
100
10
VCC = 5 V
90
I PULLUPAC (mA)
VOUT - VIN (mV)
8
80 VCC = 3.3 V OR 5.5 V 70
6 VCC = 3.3 V
4
60
2 VCC = 2.7 V 0 -40 +25 TEMPERATURE (C) +85
50
40 0 10,000 20,000 RPULLUP () 30,000 40,000
SW02346
SW02154
Figure 11. IPULLUPAC versus Temperature NOTE: 1. ICC2 (Pin 1) typical current averages 0.1 mA less than ICC on Pin 8.
Figure 13. Connection circuitry VOUT - VIN
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
TEST CIRCUIT
VCC VCC
RL = 10 k VI PULSE GENERATOR RT D.U.T. CL= 100 pF VO
DEFINITIONS
RL = Load resistor. CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to the output impedance ZO of the pulse generators.
SW02345
Figure 14. Test circuitry for switching times
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
2004 Oct 05
13
Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
2004 Oct 05
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Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
REVISION HISTORY
Rev _1 Date 20041005 Description Product data sheet (9397 750 14005).
2004 Oct 05
15
Philips Semiconductors
Product data sheet
Level shifting hot swappable I2C and SMBus buffer
PCA9512
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Level
I
Data sheet status [1]
Objective data
Product status [2] [3]
Development
Definitions
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data
Qualification
III
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2004 All rights reserved. Published in the U.S.A. Date of release: 10-04
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document number:
9397 750 14005
Philips Semiconductors
2004 Oct 05 16

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